This invention relates generally to floating gate memory devices such as an array of Flash electrically, erasable programmable read-only memory (EEPROM) cells. More particularly, the present invention relates to a control circuit for generating an accurate drain voltage for memory core cells during a Read mode of operation.
As is generally known in the art, there exists a class of non-volatile memory devices referred to as "Flash EEPROMs" which has recently emerged as an important memory device by combining the advantages of EPROM density with EEPROM electrical erasability. Such Flash EEPROMs provide electrical erasing and a small cell size. In a conventional Flash EEPROM memory device, a plurality of one-transistor core cells may be formed on a semiconductor substrate in which each cell is comprised of a P-type conductivity substrate, an N-type conductivity source region formed integrally with the substrate, and an N-type conductivity drain region also formed integrally within the substrate. A floating gate is separated from the substrate by a thin dielectric layer. A second dielectric layer separates a control gate from the floating gate. A P-type channel region in the substrate separates the source and drain regions.
One type of architecture used for Flash memories is typically referred to as a NOR Flash memory architecture which is an array of Flash EEPROM cells (floating gate devices) which are divided into a plurality of sectors. Further, the memory cells within each sector are arranged in rows of wordlines and columns of bitlines intersecting the rows of wordlines. The source region of each cell transistor within each sector is tied to a common node. Therefore, all of the cells within a particular sector can be erased simultaneously and erasure may be performed on a sector-by-sector basis. The control gates of the cell transistors are coupled to wordlines, and the drains thereof are coupled to bit lines.
In order to program the Flash EEPROM cell in conventional operation, the drain region and the control gate are raised to predetermined potentials above the potential applied to the source region. For example, the drain region has applied thereto a voltage V.sub.D of approximately +5.5 volts with the control gate V.sub.G having a voltage of approximately +9 volts applied thereto. These voltages produce "hot electrons" which are accelerated across the thin dielectric layer and onto the floating gate. This hot electron injection results in an increase of the floating gate threshold by approximately two to four volts.
For erasing the Flash EEPROM cell in conventional operation, a positive potential (e.g., +5 volts) is applied to the source region. The control gate is applied with a negative potential (e.g., -8 volts), and the drain region is allowed to float. A strong electric field develops between the floating gate and the source region, and a negative charge is extracted from the floating gate to the source region by way of Fowler-Nordheim tunneling.
In order to determine whether the Flash EEPROM cell has been properly programmed or not, the magnitude of the read current is measured. Typically, in the read mode of operation the source region is held at a ground potential (0 volts) and the control gate is held at a potential of about +5 volts. The drain region is held at a potential between +1 to +2 volts. Under these conditions, an unprogrammed cell (storing a logic "1") will conduct a current level approximately 50 to 100 .mu.A. The programmed cell (storing a logic "0") will have considerably less current flowing.
In FIG. 1, there is shown a simplified block diagram of a conventional semiconductor integrated circuit memory device 10 which includes a cell matrix 12 formed of a plurality of memory core cells MC11 . . . MCnm arranged in rows and columns. The cell matrix 12 is accessed by row address signals A.sub.i and column address signals A.sub.j. A row decoder 14 is responsive to the row address signals A.sub.i for selecting one of the wordlines WL1 . . . WLn. At the same time, a column decoder 16 is responsive to the column address signals A.sub.j for generating column selection signals CS1 . . . CSm. The gates of the column selection transistors CST1 . . . CSTm are connected to a respective one of the column selection signals CS1 . . . CSm. The drains of the column selection transistors CST1 . . . CSTm are all connected together and to a common node A. Each of the sources of the column selection transistors is coupled via respective select gate transistors SG1 . . . SGm to one of the plurality of bitlines BL1 . . . BLm which are arranged to intersect the rows of wordlines WL1 . . . WLm. The gates of the select gate transistors SG1 . . . SGm are all connected together and further connected to receive a select gate voltage SEL.
Further, each of the memory core cells MC11 . . . MCnm is comprised of one of the corresponding floating gate core cell transistors Q.sub.P11 -Q.sub.Pnm. Each of the control gates of the cores transistors is connected to one of the corresponding rows of wordlines WL1 . . . WLn, each of the drains (node D) thereof is connected to one of the corresponding columns of bitlines BL1 . . . BLm, and each of the sources thereof is connected to an array ground potential VSS. The node A is connected to an external power supply voltage VCC, which is typically in the range of +2.5 V to +3.6 V and is dependent upon temperature. The node A is also connected to a sense amplifier circuit 18 for sensing the data during the Read mode of operation.
When the data stored in a memory core cell such as the cell MC11 is to be sensed during the reading mode, the gate of the column selection transistor CST1 is set to a high voltage by the column decoder 16 and the gate of the select gate transistor SG1 is also selected to be at a high voltage. Thus, the power supply voltage VCC will be passed to the drain at the node D of the memory core transistor Q.sub.P11. At the same time, the wordline WL1 will be set to a high voltage level by the row decoder 14. As a result, the control gate and the drain of the selected memory core cell MC11 are both set to a high voltage. In this way, the data on the corresponding bitline BL1 is applied to the sense amplifier circuit 18.
In order to avoid the problem of a read disturb, it is generally known that the voltage at the drain (node D) of the selected core cell transistor must not be higher than a predetermined voltage (for example, +1.7 volts) dependent upon the technology used. If it is assumed that the read current for an erased cell is 40 .mu.A and that sixteen (16) such cells are read at once, then a total read current of 16.times.40.mu.A or 0.64 mA is required to be supplied. However, it is difficult to create an accurate voltage of +1.7 V at the node D from a power supply of only +2.6 V at the node A with a load current of 0.64 mA in a very short amount of time (about 30 nS).
In view of this, there has arisen a need of providing a way of generating an accurate drain voltage for selected memory core cells during a Read mode of operation on an efficient and effective basis. This is accomplished in the present invention by accurately controlling a select gate voltage which is applied to the gates of the select gate transistors whose sources are connected to corresponding drains of the selected memory core transistors during Read.